Low Power NAND Gate–based Half and Full Adder / Subtractor Using CMOS Technique

نویسندگان
چکیده

برای دانلود باید عضویت طلایی داشته باشید

برای دانلود متن کامل این مقاله و بیش از 32 میلیون مقاله دیگر ابتدا ثبت نام کنید

اگر عضو سایت هستید لطفا وارد حساب کاربری خود شوید

منابع مشابه

Design a Low Power Half-Subtractor Using .90μm CMOS Technology

In this paper we are presenting a Half-Subtractor using Adaptive Voltage Level (AVL) technique consuming less power than the conventional one .The main objective is to design that half subtractor using either of the two adaptive voltage level(AVL) techniques to reduce the sub threshold leakage current which plays a very important role in the reduction of power dissipation. We can bring down the...

متن کامل

Low Power Dynamic CMOS Full-Adder Cell

In this paper a new area efficient, high-speed and ultra-low power 1-bit full adder cell is presented. The performance: power, time delay and power delay product (PDP) of the proposed adder cell has been analyzed in comparison with the four existent low-power, high-speed adders. The circuits being studied are optimized for energy efficiency at 0.18-μm CMOS process technology and intensive simul...

متن کامل

A New Low Power Cmos Full Adder

Low power design of VLSI circuits has been identified as a critical technological need in recent years due to the high demand for portable consumer electronics products. In this regard many innovative designs for basic logic functions using pass transistors and transmission gates appeared in the literature recently. But they were all designed mostly by intuition and cleverness of the designer. ...

متن کامل

Design of Low Power Reduced Wallace Multiplier with Compact Carry Select Adder, Half Adder & Full Adder Using Cmos Technology

The Wallace Multiplier is mainly used in the Arithmetic & Logic Unit (ALU) to perform the scientific computation in processors, controller etc... The existing multiplication technique like booth multiplier, array multiplier etc requires more time in multiplications. Hence Wallace Multiplier has been designed by using the parallel process to reduce the delay. The regular Wallace Multiplier requi...

متن کامل

Low Power Reversible Parallel Binary Adder/Subtractor

In recent years, Reversible Logic is becoming more and more prominent technology having its applications in Low Power CMOS, Quantum Computing, Nanotechnology, and Optical Computing. Reversibility plays an important role when energy efficient computations are considered. In this paper, Reversible eight-bit Parallel Binary Adder/Subtractor with Design I, Design II and Design III are proposed. In ...

متن کامل

ذخیره در منابع من


  با ذخیره ی این منبع در منابع من، دسترسی به آن را برای استفاده های بعدی آسان تر کنید

ژورنال

عنوان ژورنال: Journal of Robotics and Control (JRC)

سال: 2021

ISSN: 2715-5056,2715-5072

DOI: 10.18196/jrc.2487